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perf: extend watch-set fingerprint cache to AVR / Teensy / other orchestrators #121

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@zackees

Follow-up from #120.

The hash_watch_set_stamps_cached wrapper + BuildParams::watch_set_cache plumbing landed in #120, but the fast-path fingerprint check that consumes it only exists in crates/fbuild-build/src/esp32/orchestrator.rs today. AVR / Teensy / RP2040 / STM32 orchestrators fall back to their own (slower) warm-path logic, so the memo never fires for them.

Scope:

  • Port the ESP32 fast-path check (lines ~329–423 of esp32/orchestrator.rs) to the AVR orchestrator as a starting point — AVR is the smallest viable testbed and has the fastest compile cycle for iteration.
  • Extract the common logic into crate::build_fingerprint::fast_path_check(...) so future orchestrators can opt in with a one-liner.
  • Sanity check: warm fbuild build tests/platform/uno -e uno should land <50 ms when the cache is fresh (today is 211 ms, dominated by the per-call orchestrator setup).

Non-goals:

  • Not redesigning the on-disk fingerprint format.
  • Not touching WASM / emulator-only orchestrators.

Related: #91 (warm-build instrumentation), #114 (warm-deploy loop), #120 (watch-set cache).

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  1. zackees commented on Apr 19, 2026

    @zackees
    MemberAuthor

    Partially addressed in #128 — AVR orchestrator now has its own fast-path check sharing the PersistedBuildFingerprint + hash_watch_set_stamps_cached primitives but without a common helper.

    Remaining scope (re-opening):

    • Extract the shared "check metadata + artifacts + watch-set → Hit/Miss" shape into crate::build_fingerprint::fast_path_check(...) with an orchestrator-specific callback for (a) the expected artifact list and (b) the BuildResult builder.
    • Port that helper to Teensy / RP2040 / STM32. The ESP32 path has zccache-first branching that should stay out of the generic helper — AVR is the right pattern to generalize from.
    • Decide whether to also port back into the ESP32 orchestrator or keep the ESP32 variant as the "full-featured" one (zccache + selective regions + 5 artifacts).

    Each port is independent — can land as separate PRs.

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