can not correctly generate code, seems opecnode will write large codes then failed #16816

Activity

1. simonjhy

   added

   bugSomething isn't workingSomething isn't working

   on Mar 10, 2026
2. github-actions

   assigned

   thdxr

   on Mar 10, 2026
3. github-actions

   added

   coreAnything pertaining to core functionality of the application (opencode server stuff)Anything pertaining to core functionality of the application (opencode server stuff)

   windows

   on Mar 10, 2026
4. github-actions commented on Mar 10, 2026

   

   github-actionsBot

   on Mar 10, 2026 – with GitHub Actions

   Contributor

   More actions

   This issue might be a duplicate of existing issues. Please check:

   • 🐛 Bug Report: MCP Tool JSON Parsing Errors on OpenCode (GLM-4.7) #8102: MCP Tool JSON Parsing Errors on OpenCode (GLM-4.7) - same model and same JSON parsing errors
   • [bug] GLM 5 keeps screwing up the json parsing of read tool calling #13982: GLM 5 keeps screwing up the json parsing of read tool calling - same model family, same issue type
   • [Bug] JSON Parse Error with Zhipu GLM-4.7: Stream chunks are concatenated incorrectly #7692: JSON Parse Error with Zhipu GLM-4.7: Stream chunks are concatenated incorrectly - same model, JSON parsing during streaming
   • Write tool JSON parsing error with large files and special characters #11630: Write tool JSON parsing error with large files and special characters - same symptom when writing files with special characters (C code)
5. simonjhy commented on Mar 19, 2026

   

   simonjhy

   on Mar 19, 2026

   Author

   More actions

   ⚙ invalid [tool=write, error=Invalid input for tool write: JSON parsing failed: Text: {"content": "/**\n ******************************************************************************\n * @file adc1_hal.c\n * @brief HAL Driver Implementation for SLM32F1XA001 ADC1 peripheral\n * @Version 1.0.0\n * @Date 2026-03-19\n *\n * @note\n * This implementation follows MISRA-C:2023 guidelines with strict\n * adherence to:\n * - Register access via local copy pattern (read-modify-write)\n * - No bit-shift operations or magic numbers\n * - Explicit type casting\n * - Volatile register access\n * - Parameter validation and state management\n *\n *********************\n /\n\n#include "adc1_hal.h"\n#include <string.h>\n\n/===========================================================/\n/ PUBLIC VARIABLES /\n/===========================================================/\n\nvolatile ADC1_InitTypeDef g_ADC1;\nvolatile ADC_SequenceConfigTypeDef g_ADC1_SeqAConfig;\nvolatile ADC_SequenceConfigTypeDef g_ADC1_SeqBConfig;\nvolatile ADC_SequenceConfigTypeDef g_ADC1_SeqCConfig;\nvolatile uint8_t g_ADC1_ChannelSelection[16] = {0};\nvolatile ADC_StateTypeDef g_ADC1_State = ADC_STATE_IDLE;\nvolatile uint32_t g_ADC1_ErrorCode = 0;\n\n/===========================================================/\n/ LOCAL MACRO DEFINITIONS /\n/===========================================================/\n\n#define ADC1_ISR_PRIORITY_NUM (5U)\n#define ADC1_ISR_SUB_PRIORITY_NUM (0U)\n\n#define NULL_CHECK(ptr) \\n do { \\n if ((ptr) == NULL) { \\n g_ADC1_ErrorCode = HAL_INVALID_PARAM; \\n return HAL_INVALID_PARAM; \\n } \\n } while(0)\n\n#define INIT_SEQUENCE(sequence, numChannels, maxConverts) \\n do { \\n (sequence).sequence = (sequence); \\n (sequence).chSelection = &(g_ADC1_ChannelSelection); \\n (sequence).count = maxConverts; \\n memset(&(sequence).trigSrc), 0, sizeof(ADC_TriggerSrcTypeDef)); \\n (sequence).singleShot = false; \\n (sequence).watchdog_LT = 0; \\n (sequence).watchdog_HT = 0; \\n (sequence).dmaEnabled = false; \\n (sequence).accumulationEnabled = false; \\n (sequence).accumulationNum = 0; \\n (sequence).userParam = NULL; \\n } while(0)\n\n/===========================================================/\n/ LOCAL FUNCTION PROTOTYPES /\n/===========================================================/\n\nstatic HAL_StatusTypeDef ADC1_SetClockDiv(uint8_t div);\nstatic HAL_StatusTypeDef ADC1_Enable(uint8_t enable);\nstatic HAL_StatusTypeDef ADC1_SequenceStart(uint8_t seqNum);\nstatic HAL_StatusTypeDef ADC1_SequenceAbort(uint8_t seqNum, uint8_t saveCurrent);\nstatic uint16_t ADC1_ReadRegister(__IO uint32_t addr);\nstatic HAL_StatusTypeDef ADC1_WriteRegister(__IO uint32_t addr, uint32_t value);\nstatic uint8_t ADC1_MapTrigSource(ADC_TriggerSrcTypeDef trig);\nstatic void ADC1_ProcessInterrupt(ADC_SequenceTypeDef sequence);\n\n/===========================================================/\n/ 1. LIFECYCLE FUNCTIONS /\n/===========================================================/\n\nHAL_StatusTypeDef HAL_ADC1_Init(const ADC1_InitTypeDef config)\n{\n uint32_t reg;\n ADC1_IE0_TypeDef ie0;\n ADC1_IE1_TypeDef ie1;\n\n if (config == NULL)\n {\n g_ADC1_ErrorCode = HAL_INVALID_PARAM;\n return HAL_INVALID_PARAM;\n }\n\n if (HAL_ADC1_GetState() != ADC_STATE_IDLE)\n {\n g_ADC1_ErrorCode = HAL_BUSY;\n return HAL_BUSY;\n }\n\n / Initialize global configuration /\n memset(&g_ADC1, 0, sizeof(ADC1_InitTypeDef));\n memcpy(&g_ADC1, config, sizeof(ADC1_InitTypeDef));\n\n / Reset sequence configurations /\n memset(&g_ADC1_SeqAConfig, 0, sizeof(ADC1_SequenceConfigTypeDef));\n memset(&g_ADC1_SeqBConfig, 0, sizeof(ADC1_SequenceConfigTypeDef));\n memset(&g_ADC1_SeqCConfig, 0, sizeof(ADC1_SequenceConfigTypeDef));\n memset(g_ADC1_ChannelSelection, 0, sizeof(g_ADC1_ChannelSelection));\n\n / Configure clock divider /\n reg = ADC1_SetClockDiv((uint8_t)config->clockDiv);\n if (reg != HAL_OK)\n {\n return reg;\n }\n\n / Set result alignment /\n reg = ADC1_READ_REG(ADC1_CR0);\n reg.B.RES_ALIGN = (uint32_t)config->resultAlign;\n if (ADC1_WRITE_REG(ADC1_CR0, reg.U) != HAL_OK)\n {\n return HAL_ERROR;\n }\n\n / Set high priority sequence as default /\n g_ADC1.autoSeq = ADC_SEQ_A;\n\n / Initialize global state /\n g_ADC1_State = ADC_STATE_ENABLED;\n\n / Clear all error code /\n g_ADC1_ErrorCode = HAL_OK;\n\n return HAL_OK;\n}\n\nHAL_StatusTypeDef HAL_ADC1_DeInit(void)\n{\n ADC1_CR0_TypeDef cr0;\n ADC1_CR1_TypeDef cr1;\n\n if (HAL_ADC1_GetState() == ADC_STATE_IDLE)\n {\n return HAL_OK;\n }\n\n / Disable ADC to halt any conversions /\n cr0.U = ADC1_READ_REG(ADC1_CR0);\n cr0.B.ADC_EN = 0U;\n if (ADC1_WRITE_REG(ADC1_CR0, cr0.U) != HAL_OK)\n {\n return HAL_ERROR;\n }\n\n / Reset clock divider /\n cr1.U = ADC1_READ_REG(ADC1_CR1);\n cr1.B.CLK_REV = 0U;\n cr1.B.CLK_EN = 0U;\n cr1.B.CLK_SEL = (uint32_t)(ADC_DIV_1);\n if (ADC1_WRITE_REG(ADC1_CR1, cr1.U) != HAL_OK)\n {\n return HAL_ERROR;\n }\n\n / Reset sequence configuration registers /\n memset(&g_ADC1_SeqAConfig, 0, sizeof(ADC1_SequenceConfigTypeDef));\n memset(&g_ADC1_SeqBConfig, 0, sizeof(ADC1_SequenceConfigTypeDef));\n memset(&g_ADC1_SeqCConfig, 0, sizeof(ADC1_SequenceConfigTypeDef));\n memset(g_ADC1_ChannelSelection, 0, sizeof(g_ADC1_ChannelSelection));\n\n / Reset global state /\n g_ADC1_State = ADC_STATE_IDLE;\n g_ADC1_ErrorCode = HAL_OK;\n\n return HAL_OK;\n}\n\nHAL_StatusTypeDef HAL_ADC1_Enable(void)\n{\n ADC1_CR0_TypeDef cr0;\n ADC1_CR2_TypeDef cr2;\n\n if (HAL_ADC1_GetState() == ADC_STATE_IDLE)\n {\n g_ADC1_ErrorCode = HAL_NOT_READY;\n return HAL_NOT_READY;\n }\n\n / Enable ADC module /\n cr0.U = ADC1_READ_REG(ADC1_CR0);\n cr0.B.ADC_EN = 1U;\n if (ADC1_WRITE_REG(ADC1_CR0, cr0.U) != HAL_OK)\n {\n return HAL_ERROR;\n }\n\n / Set result data read parameters based on mode /\n cr2.U = ADC1_READ_REG(ADC1_CR2);\n cr2.B.RD_START = (uint32_t)g_ADC1.rdStart;\n cr2.B.RD_RANGE = (uint32_t)g_ADC1.rdRange;\n if (ADC1_WRITE_REG(ADC1_CR2, cr2.U) != HAL_OK)\n {\n return HAL_ERROR;\n }\n\n / Clear existing interrupts /\n ie0.U = 0U;\n ie1.U = 0U;\n ADC1_WRITE_REG(ADC1_IE0, ie0.U);\n ADC1_WRITE_REG(ADC1_IE1, ie1.U);\n\n / Enable ADC /\n g_ADC1_State = ADC_STATE_ENABLED;\n\n return HAL_OK;\n}\n\nHAL_StatusTypeDef HAL_ADC1_Disable(void)\n{\n ADC1_CR0_TypeDef cr0;\n\n / Disable ADC module /\n cr0.U = ADC1_READ_REG(ADC1_CR0);\n cr0.B.ADC_EN = 0U;\n if (ADC1_WRITE_REG(ADC1_CR0, cr0.U) != HAL_OK)\n {\n return HAL_ERROR;\n }\n\n / Update state /\n if (cr0.B.SEQA_WORK == 0U && cr0.B.SEQB_WORK == 0U && cr0.B.SEQC_WORK == 0U)\n {\n g_ADC1_State = ADC_STATE_IDLE;\n }\n else\n {\n g_ADC1_State = ADC_STATE_BUSY;\n }\n\n return HAL_OK;\n}\n\n/===========================================================/\n/ 2. SEQUENCE CONFIGURATION FUNCTIONS /\n/===========================================================/\n\nHAL_StatusTypeDef HAL_ADC1_ConfigSequence(const ADC1_SequenceConfigTypeDef sequenceConfig)\n{\n HAL_StatusTypeDef status;\n uint32_t ctrlReg;\n uint8_t numChannels;\n uint8_t seqNum;\n uint8_t chIndex;\n\n if (sequenceConfig == NULL)\n {\n g_ADC1_ErrorCode = HAL_INVALID_PARAM;\n return HAL_INVALID_PARAM;\n }\n\n if (HAL_ADC1_GetState() == ADC_STATE_ERROR || HAL_ADC1_GetState() == ADC_STATE_TIMEOUT)\n {\n g_ADC1_ErrorCode = HAL_NOT_READY;\n return HAL_NOT_READY;\n }\n\n seqNum = (uint8_t)sequenceConfig->sequence;\n\n switch(seqNum)\n {\n case ADC_SEQ_A:\n numChannels = 16U;\n g_ADC1_SeqAConfig = sequenceConfig;\n break;\n\n case ADC_SEQ_B:\n numChannels = 8U;\n g_ADC1_SeqBConfig = sequenceConfig;\n break;\n\n case ADC_SEQ_C:\n numChannels = 1U;\n g_ADC1_SeqCConfig = sequenceConfig;\n break;\n\n default:\n g_ADC1_ErrorCode = HAL_INVALID_PARAM;\n return HAL_INVALID_PARAM;\n }\n\n / Configure sequence triggers and count /\n switch(seqNum)\n {\n case ADC_SEQ_A:\n / Clear existing trigger and mode settings /\n ctrlReg = ADC1_READ_REG(ADC1_SEQA_CR);\n ctrlReg.B.INTEN_TRIG_EN = 0U;\n ctrlReg.B.SEQA_SINGLY = (uint32_t)sequenceConfig->singleShot;\n ctrlReg.B.SEQA_NUM = ((uint32_t)sequenceConfig->count - 1U);\n ADC1_WRITE_REG(ADC1_SEQA_CR, ctrlReg);\n\n / Configure channel selections /\n for (chIndex = 0; chIndex < numChannels; chIndex++)\n {\n ADC1_WRITE_REG(ADC1_SEQA_CR0 + (chIndex * 4U),\n (uint32_t)(sequenceConfig->chSelection[chIndex] & 0x1FU));\n }\n break;\n\n case ADC_SEQ_B:\n ctrlReg = ADC1_READ_REG(ADC1_SEQB_CR);\n ctrlReg.B.INTEN_TRIG_EN = 0U;\n ctrlReg.B.SEQB_SINGLY = (uint32_t)sequenceConfig->singleShot;\n ctrlReg.B.SEQB_NUM = ((uint32_t)sequenceConfig->count - 1U);\n ADC1_WRITE_REG(ADC1_SEQB_CR, ctrlReg);\n\n for (chIndex = 0; chIndex < numChannels; chIndex++)\n {\n ADC1_WRITE_REG(ADC1_SEQB_CR0 + (chIndex * 4U),\n (uint32_t)(sequenceConfig->chSelection[chIndex] & 0x1FU));\n }\n break;\n\n case ADC_SEQ_C:\n ctrlReg = ADC1_READ_REG(ADC1_SEQC_CR);\n ctrlReg.B.INTEN_TRIG_EN = 0U;\n ctrlReg.B.SEQC_SINGLY = (uint32_t)sequenceConfig->singleShot;\n ADC1_WRITE_REG(ADC1_SEQC_CR, ctrlReg);\n\n ADC1_WRITE_REG(ADC1_SEQC_CR0,\n (uint32_t)(sequenceConfig->chSelection[0] & 0x1FU));\n break;\n }\n\n status = HAL_ADC1_SetClockDiv((uint8_t)sequenceConfig->trigSrc);\n if (status != HAL_OK)\n {\n return status;\n }\n\n return HAL_OK;\n}\n\nHAL_StatusTypeDef HAL_ADC1_ConfigSequenceChannel(ADC_SequenceTypeDef sequence,\n uint8_t channel,\n uint8_t position)\n{\n uint32_t reg;\n\n if (channel > 31U || position > 15U)\n {\n g_ADC1_ErrorCode = HAL_INVALID_PARAM;\n return HAL_INVALID_PARAM;\n }\n\n switch(sequence)\n {\n case ADC_SEQ_A:\n if (position >= 16U)\n {\n g_ADC1_ErrorCode = HAL_INVALID_PARAM;\n return HAL_INVALID_PARAM;\n }\n reg = ADC1_READ_REG(ADC1_SEQA_CR0 + (position * 4U));\n reg.B.SEQA_CH_SEL0 = (uint32_t)channel;\n ADC1_WRITE_REG(ADC1_SEQA_CR0 + (position * 4U), reg.U);\n g_ADC1_ChannelSelection[position] = (uint8_t)channel;\n break;\n\n case ADC_SEQ_B:\n if (position >= 8U)\n {\n g_ADC1_ErrorCode = HAL_INVALID_PARAM;\n return HAL_INVALID_PARAM;\n }\n reg = ADC1_READ_REG(ADC1_SEQB_CR0 + (position * 4U));\n reg.B.SEQB_CH_SEL0 = (uint32_t)channel;\n ADC1_WRITE_REG(ADC1_SEQB_CR0 + (position * 4U), reg.U);\n g_ADC1_ChannelSelection[position] = (uint8_t)channel;\n break;\n\n case ADC_SEQ_C:\n if (position != 0U)\n {\n g_ADC1_ErrorCode = HAL_INVALID_PARAM;\n return HAL_INVALID_PARAM;\n }\n reg = ADC1_READ_REG(ADC1_SEQC_CR0);\n reg.B.SEQC_CH_SEL0 = (uint32_t)channel;\n ADC1_WRITE_REG(ADC1_SEQC_CR0, reg.U);\n g_ADC1_ChannelSelection[0] = (uint8_t)channel;\n break;\n\n default:\n g_ADC1_ErrorCode = HAL_INVALID_PARAM;\n return HAL_INVALID_PARAM;\n }\n\n return HAL_OK;\n}\n\n/===========================================================/\n/ 3. OPERATION FUNCTIONS /\n/===========================================================/\n\nHAL_StatusTypeDef HAL_ADC1_Start(ADC_SequenceTypeDef sequence)\n{\n uint32_t reg;\n ADC_SequenceConfigTypeDef seqConfig;\n\n seqConfig = NULL;\n\n switch(sequence)\n {\n case ADC_SEQ_A:\n seqConfig = &g_ADC1_SeqAConfig;\n reg = ADC1_READ_REG(ADC1_SEQA_CR);\n reg.B.INTEN_TRIG_EN = 1U;\n ADC1_WRITE_REG(ADC1_SEQA_CR, reg.U);\n break;\n\n case ADC_SEQ_B:\n seqConfig = &g_ADC1_SeqBConfig;\n reg = ADC1_READ_REG(ADC1_SEQB_CR);\n reg.B.INTEN_TRIG_EN = 1U;\n ADC1_WRITE_REG(ADC1_SEQB_CR, reg.U);\n break;\n\n case ADC_SEQ_C:\n seqConfig = &g_ADC1_SeqCConfig;\n reg = ADC1_READ_REG(ADC1_SEQC_CR);\n reg.B.INTEN_TRIG_EN = 1U;\n ADC1_WRITE_REG(ADC1_SEQC_CR, reg.U);\n break;\n\n default:\n g_ADC1_ErrorCode = HAL_INVALID_PARAM;\n return HAL_INVALID_PARAM;\n }\n\n if (HAL_ADC1_IsSequenceWorking(sequence))\n {\n g_ADC1_ErrorCode = HAL_BUSY;\n return HAL_BUSY;\n }\n\n return ADC1_SequenceStart((uint8_t)sequence);\n}\n\nHAL_StatusTypeDef HAL_ADC1_Stop(ADC_SequenceTypeDef sequence)\n{\n uint32_t ctrlReg;\n bool saveCurrent = true;\n\n switch(sequence)\n {\n case ADC_SEQ_A:\n ctrlReg = ADC1_READ_REG(ADC1_CR0);\n ctrlReg.B.ABORT = 1U;\n ctrlReg.B.ABORT_MODE = (uint32_t)saveCurrent;\n ADC1_WRITE_REG(ADC1_CR0, ctrlReg.U);\n break;\n\n case ADC_SEQ_B:\n ctrlReg = ADC1_READ_REG(ADC1_CR0);\n ctrlReg.B.ABORT = 1U;\n ctrlReg.B.ABORT_MODE = (uint32_t)saveCurrent;\n ADC1_WRITE_REG(ADC1_CR0, ctrlReg.U);\n break;\n\n case ADC_SEQ_C:\n g_ADC1_ErrorCode = HAL_NOT_SUPPORTED;\n return HAL_NOT_SUPPORTED;\n\n default:\n g_ADC1_ErrorCode = HAL_INVALID_PARAM;\n return HAL_INVALID_PARAM;\n }\n\n return HAL_OK;\n}\n\nHAL_StatusTypeDef HAL_ADC1_SingleConversion(ADC_SequenceTypeDef sequence, uint8_t channel)\n{\n if (channel > 31U)\n {\n g_ADC1_ErrorCode = HAL_INVALID_PARAM;\n return HAL_INVALID_PARAM;\n }\n\n if (HAL_ADC1_IsSequenceWorking(sequence))\n {\n g_ADC1_ErrorCode = HAL_BUSY;\n return HAL_BUSY;\n }\n\n return HAL_ADC1_Start(sequence);\n}\n\nHAL_StatusTypeDef HAL_ADC1_EnableDMA(ADC_SequenceTypeDef sequence)\n{\n ADC1_CR0_TypeDef cr0;\n\n switch(sequence)\n {\n case ADC_SEQ_A:\n cr0.U = ADC1_READ_REG(ADC1_CR0);\n cr0.B.SEQA_DMA_EN = 1U;\n ADC1_WRITE_REG(ADC1_CR0, cr0.U);\n break;\n\n case ADC_SEQ_B:\n cr0.U = ADC1_READ_REG(ADC1_CR0);\n cr0.B.SEQB_DMA_EN = 1U;\n ADC1_WRITE_REG(ADC1_CR0, cr0.U);\n break;\n\n case ADC_SEQ_C:\n cr0.U = ADC1_READ_REG(ADC1_CR0);\n cr0.B.SEQC_DMA_EN = 1U;\n ADC1_WRITE_REG(ADC1_CR0, cr0.U);\n break;\n\n default:\n return HAL_INVALID_PARAM;\n }\n\n return HAL_OK;\n}\n\nHAL_StatusTypeDef HAL_ADC1_DisableDMA(ADC_SequenceTypeDef sequence)\n{\n ADC1_CR0_TypeDef cr0;\n\n switch(sequence)\n {\n case ADC_SEQ_A:\n cr0.U = ADC1_READ_REG(ADC1_CR0);\n cr0.B.SEQA_DMA_EN = 0U;\n ADC1_WRITE_REG(ADC1_CR0, cr0.U);\n break;\n\n case ADC_SEQ_B:\n cr0.U = ADC1_READ_REG(ADC1_CR0);\n cr0.B.SEQB_DMA_EN = 0U;\n ADC1_WRITE_REG(ADC1_CR0, cr0.U);\n break;\n\n case ADC_SEQ_C:\n cr0.U = ADC1_READ_REG(ADC1_CR0);\n cr0.B.SEQC_DMA_EN = 0U;\n ADC1_WRITE_REG(ADC1_CR0, cr0.U);\n break;\n\n default:\n return HAL_INVALID_PARAM;\n }\n\n return HAL_OK;\n}\n\n/===========================================================/\n/ 4. INTERRUPT & CALLBACK FUNCTIONS /\n/===========================================================/\n\nHAL_StatusTypeDef HAL_ADC1_RegisterCallback(ADC_SequenceTypeDef sequence,\n ADC1_CallbackFunc callback,\n void param)\n{\n switch(sequence)\n {\n case ADC_SEQ_A:\n g_ADC1_SeqAConfig.userParam = param;\n break;\n\n case ADC_SEQ_B:\n g_ADC1_SeqBConfig.userParam = param;\n break;\n\n case ADC_SEQ_C:\n g_ADC1_SeqCConfig.userParam = param;\n break;\n\n default:\n g_ADC1_ErrorCode = HAL_INVALID_PARAM;\n return HAL_INVALID_PARAM;\n }\n\n return HAL_OK;\n}\n\n/===========================================================/\n/ 5. POLLING FUNCTIONS /\n/===========================================================/\n\nHAL_StatusTypeDef HAL_ADC1_PollConversionComplete(ADC_SequenceTypeDef sequence,\n uint32_t timeoutMs)\n{\n uint32_t timeoutStart;\n ADC1_IF0_TypeDef if0;\n ADC1_IF1_TypeDef if1;\n uint32_t timeoutCount;\n uint32_t timeoutThreshold;\n\n timeoutThreshold = (timeoutMs / 5000U) + 1U;\n timeoutStart = GetTick();\n\n if (sequence != ADC_SEQ_A && sequence != ADC_SEQ_B && sequence != ADC_SEQ_C)\n {\n g_ADC1_ErrorCode = HAL_INVALID_PARAM;\n return HAL_INVALID_PARAM;\n }\n\n timeoutCount = 0U;\n\n while (timeoutCount < timeoutThreshold)\n {\n if (sequence == ADC_SEQ_A)\n {\n if0.U = ADC1_READ_REG(ADC1_IF0);\n if (if0.B.INTSTS_SEQA_1CH != 0U)\n {\n return HAL_OK;\n }\n if (if0.B.INTSTS_SEQA_HSEQ != 0U)\n {\n return HAL_OK;\n }\n }\n else if (sequence == ADC_SEQ_B)\n {\n if0.U = ADC1_READ_REG(ADC1_IF0);\n if (if0.B.INTSTS_SEQB_1CH != 0U)\n {\n return HAL_OK;\n }\n }\n else if (sequence == ADC_SEQ_C)\n {\n if0.U = ADC1_READ_REG(ADC1_IF0);\n if (if0.B.INTSTS_SEQC_1CH != 0U)\n {\n return HAL_OK;\n }\n }\n\n if (HAL_ADC1_IsTriggerOverrun(sequence))\n {\n g_ADC1_ErrorCode = HAL_TIMEOUT;\n return HAL_TIMEOUT;\n }\n\n timeoutCount++;\n }\n\n g_ADC1_ErrorCode = HAL_TIMEOUT;\n return HAL_TIMEOUT;\n}\n\nHAL_StatusTypeDef HAL_ADC1_PollSequenceComplete(ADC_SequenceTypeDef sequence,\n uint32_t timeoutMs)\n{\n uint32_t timeoutStart;\n ADC1_IF0_TypeDef if0;\n ADC1_IF1_TypeDef if1;\n uint32_t timeoutCount;\n uint32_t timeoutThreshold;\n\n timeoutThreshold = (timeoutMs / 5000U) + 1U;\n timeoutStart = GetTick();\n\n if (sequence != ADC_SEQ_A && sequence != ADC_SEQ_B && sequence != ADC_SEQ_C)\n {\n g_ADC1_ErrorCode = HAL_INVALID_PARAM;\n return HAL_INVALID_PARAM;\n }\n\n timeoutCount = 0U;\n\n while (timeoutCount < timeoutThreshold)\n {\n if (sequence == ADC_SEQ_A)\n {\n if0.U = ADC1_READ_REG(ADC1_IF0);\n if (if0.B.INTSTS_SEQA_1SEQ != 0U)\n {\n return HAL_OK;\n }\n if (if0.B.INTSTS_SEQA_AWD0_REG != 0U)\n {\n return HAL_OK;\n }\n }\n else if (sequence == ADC_SEQ_B)\n {\n if0.U = ADC1_READ_REG(ADC1_IF0);\n if (if0.B.INTSTS_SEQB_1SEQ != 0U)\n {\n return HAL_OK;\n }\n if (if0.B.INTSTS_SEQB_AWD0_REG != 0U)\n {\n return HAL_OK;\n }\n }\n else if (sequence == ADC_SEQ_C)\n {\n if0.U = ADC1_READ_REG(ADC1_IF0);\n if (if0.B.INTSTS_SEQC_ALL != 0U)\n {\n return HAL_OK;\n }\n if (if0.B.INTSTS_SEQC_AWD0_REG != 0U)\n {\n return HAL_OK;\n }\n }\n\n timeoutCount++;\n }\n\n g_ADC1_ErrorCode = HAL_TIMEOUT;\n return HAL_TIMEOUT;\n}\n\n/===========================================================/\n/ 6. READ FUNCTIONS /\n/===========================================================/\n\nuint16_t HAL_ADC1_ReadConversionResult(ADC_SequenceTypeDef sequence, uint8_t channel)\n{\n volatile uint32_t drReg;\n\n if (sequence != ADC_SEQ_A && sequence != ADC_SEQ_B && sequence != ADC_SEQ_C)\n {\n return 0U;\n }\n\n drReg = 0U;\n\n switch(sequence)\n {\n case ADC_SEQ_A:\n drReg = ADC1_READ_REG(ADC1_SEQA_DR);\n break;\n\n case ADC_SEQ_B:\n drReg = ADC1_READ_REG(ADC1_SEQB_DR);\n break;\n\n case ADC_SEQ_C:\n drReg = ADC1_READ_REG(ADC1_SEQC_DR);\n break;\n }\n\n if (drReg != 0U)\n {\n return (uint16_t)(drReg & 0xFFFFU);\n }\n\n return 0U;\n}\n\nuint32_t HAL_ADC1_ReadAccumulationResult(void)\n{\n return (uint32_t)(ADC1_READ_REG(ADC1_ACCR) & 0xFFFFU);\n}\n\nuint16_t HAL_ADC1_ReadResult(ADC_SequenceTypeDef sequence, uint16_t resultIndex)\n{\n uint32_t reg;\n\n if (resultIndex > 15U)\n {\n return 0U;\n }\n\n switch(sequence)\n {\n case ADC_SEQ_A:\n reg = ADC1_READ_REG(ADC1_SEQA_DR0 + (resultIndex * 4U));\n break;\n\n case ADC_SEQ_B:\n reg = ADC1_READ_REG(ADC1_SEQB_DR0 + (resultIndex * 4U));\n break;\n\n case ADC_SEQ_C:\n return 0U;\n\n default:\n return 0U;\n }\n\n return (uint16_t)(reg & 0xFFFFU);\n}\n\n/===========================================================/\n/ 7. ACCUMULATION FUNCTIONS /\n/===========================================================/\n\nHAL_StatusTypeDef HAL_ADC1_EnableAccumulation(ADC_SequenceTypeDef sequence,\n uint8_t numCount,\n bool mode)\n{\n ADC1_CR0_TypeDef cr0;\n ADC1_CR2_TypeDef cr2;\n\n if (sequence != ADC_SEQ_A)\n {\n g_ADC1_ErrorCode = HAL_INVALID_PARAM;\n return HAL_INVALID_PARAM;\n }\n\n cr0.U = ADC1_READ_REG(ADC1_CR0);\n cr0.B.SEQA_ACC_EN = 1U;\n cr0.B.SEQA_ACC_MODE = (uint32_t)mode;\n ADC1_WRITE_REG(ADC1_CR0, cr0.U);\n\n cr2.U = ADC1_READ_REG(ADC1_CR2);\n cr2.B.SEQA_ACC_NUM = (uint32_t)numCount;\n ADC1_WRITE_REG(ADC1_CR2, cr2.U);\n\n return HAL_OK;\n}\n\nHAL_StatusTypeDef HAL_ADC1_ClearAccumulation(void)\n{\n ADC1_CR0_TypeDef cr0;\n\n cr0.U = ADC1_READ_REG(ADC1_CR0);\n cr0.B.SEQA_ACCR_CLR = 1U;\n if (ADC1_WRITE_REG(ADC1_CR0, cr0.U) != HAL_OK)\n {\n return HAL_ERROR;\n }\n\n return HAL_OK;\n}\n\n/===========================================================/\n/ 8. ABORTION FUNCTIONS /\n/===========================================================/\n\nHAL_StatusTypeDef HAL_ADC1_Abort(bool saveCurrentResult)\n{\n ADC1_CR0_TypeDef cr0;\n\n cr0.U = ADC1_READ_REG(ADC1_CR0);\n cr0.B.ABORT = 1U;\n cr0.B.ABORT_MODE = (uint32_t)saveCurrentResult;\n if (ADC1_WRITE_REG(ADC1_CR0, cr0.U) != HAL_OK)\n {\n return HAL_ERROR;\n }\n\n return HAL_OK;\n}\n\n/===========================================================/\n/ 9. WATCHDOG FUNCTIONS /\n/===========================================================/\n\nHAL_StatusTypeDef HAL_ADC1_ConfigWatchdog(ADC_SequenceTypeDef sequence,\n int16_t lowThreshold,\n int16_t highThreshold)\n{\n volatile uint32_t awdCrReg;\n\n awdCrReg = 0U;\n\n switch(sequence)\n {\n case ADC_SEQ_A:\n awdCrReg = ADC1_BASE + ADC1_SEQA_AWD0_CR_OFFSET;\n break;\n\n case ADC_SEQ_B:\n awdCrReg = ADC1_BASE + ADC1_SEQB_AWD0_CR_OFFSET;\n break;\n\n case ADC_SEQ_C:\n awdCrReg = ADC1_BASE + ADC1_SEQC_AWD0_CR_OFFSET;\n break;\n\n default:\n g_ADC1_ErrorCode = HAL_INVALID_PARAM;\n return HAL_INVALID_PARAM;\n }\n\n ADC1_WRITE_REG(awdCrReg, (highThreshold & 0x0FFFU) << 16U);\n ADC1_WRITE_REG(awdCrReg + 4U, (uint32_t)(lowThreshold & 0x0FFFU));\n\n return HAL_OK;\n}\n\nHAL_StatusTypeDef HAL_ADC1_EnableWatchdogInterrupt(ADC_SequenceTypeDef sequence,\n bool enableLowThresh,\n bool enableHighThresh,\n bool enableInRange)\n{\n ADC1_IE1_TypeDef ie1;\n\n ie1.U = ADC1_READ_REG(ADC1_IE1);\n\n switch(sequence)\n {\n case ADC_SEQ_A:\n ie1.B.INTEN_SEQA_AWD0_LT = (uint32_t)enableLowThresh;\n ie1.B.INTEN_SEQA_AWD0_HT = (uint32_t)enableHighThresh;\n ie1.B.INTEN_SEQA_AWD0_REG = (uint32_t)enableInRange;\n break;\n\n case ADC_SEQ_B:\n ie1.B.INTEN_SEQB_AWD0_LT = (uint32_t)enableLowThresh;\n ie1.B.INTEN_SEQB_AWD0_HT = (uint32_t)enableHighThresh;\n ie1.B.INTEN_SEQB_AWD0_REG = (uint32_t)enableInRange;\n break;\n\n case ADC_SEQ_C:\n ie1.B.INTEN_SEQC_AWD0_LT = (uint32_t)enableLowThresh;\n ie1.B.INTEN_SEQC_AWD0_HT = (uint32_t)enableHighThresh;\n ie1.B.INTEN_SEQC_AWD0_REG = (uint32_t)enableInRange;\n break;\n\n default:\n g_ADC1_ErrorCode = HAL_INVALID_PARAM;\n return HAL_INVALID_PARAM;\n }\n\n ADC1_WRITE_REG(ADC1_IE1, ie1.U);\n\n return HAL_OK;\n}\n\n/===========================================================/\n/ 10. TRIGGER FUNCTIONS /\n/===========================================================/\n\nHAL_StatusTypeDef HAL_ADC1_ConfigTrigger(ADC_SequenceTypeDef sequence,\n ADC_TriggerSrcTypeDef trigSrc)\n{\n ADC1_CR2_TypeDef cr2;\n\n cr2.U = ADC1_READ_REG(ADC1_CR2);\n cr2.B.RD_START = (uint32_t)g_ADC1.rdStart;\n cr2.B.RD_RANGE = (uint32_t)g_ADC1.rdRange;\n\n if (sequence != ADC_SEQ_A && sequence != ADC_SEQ_B && sequence != ADC_SEQ_C)\n {\n g_ADC1_ErrorCode = HAL_INVALID_PARAM;\n return HAL_INVALID_PARAM;\n }\n\n / Note: TRIG_EXT_CONFIG registers are AFE-side, not directly accessible /\n / External trigger configuration is done via TRGMUX module /\n\n return HAL_OK;\n}\n\n/===========================================================/\n/ 11. DEBUG FUNCTIONS /\n/===========================================================/\n\nHAL_StatusTypeDef HAL_ADC1_EnableDebug(ADC_SequenceTypeDef sequence)\n{\n volatile uint32_t cr0Reg;\n\n cr0Reg = ADC1_BASE + ADC1_CR0_OFFSET;\n\n switch(sequence)\n {\n case ADC_SEQ_A:\n ADC1_WRITE_REG(cr0Reg, (uint32_t)(ADC1_READ_REG(cr0Reg) | 0x00200000U));\n break;\n\n case ADC_SEQ_B:\n ADC1_WRITE_REG(cr0Reg, (uint32_t)(ADC1_READ_REG(cr0Reg) | 0x00100000U));\n break;\n\n case ADC_SEQ_C:\n ADC1_WRITE_REG(cr0Reg, (uint32_t)(ADC1_READ_REG(cr0Reg) | 0x00800000U));\n break;\n\n default:\n g_ADC1_ErrorCode = HAL_INVALID_PARAM;\n return HAL_INVALID_PARAM;\n }\n\n return HAL_OK;\n}\n\nHAL_StatusTypeDef HAL_ADC1_DisableDebug(ADC_SequenceTypeDef sequence)\n{\n volatile uint32_t cr0Reg;\n\n cr0Reg = ADC1_BASE + ADC1_CR0_OFFSET;\n\n switch(sequence)\n {\n case ADC_SEQ_A:\n ADC1_WRITE_REG(cr0Reg, (uint32_t)(ADC1_READ_REG(cr0Reg) & 0xFFDFFFFFU));\n break;\n\n case ADC_SEQ_B:\n ADC1_WRITE_REG(cr0Reg, (uint32_t)(ADC1_READ_REG(cr0Reg) & 0xFFEFFFFFU));\n break;\n\n case ADC_SEQ_C:\n ADC1_WRITE_REG(cr0Reg, (uint32_t)(ADC1_READ_REG(cr0Reg) & 0xFFF7FFFFFU));\n break;\n\n default:\n g_ADC1_ErrorCode = HAL_INVALID_PARAM;\n return HAL_INVALID_PARAM;\n }\n\n return HAL_OK;\n}\n\n/===========================================================/\n/ 12. CALIBRATION FUNCTIONS /\n/===========================================================/\n\nHAL_StatusTypeDef HAL_ADC1_EnableCalibration(uint32_t channels)\n{\n ADC1_CH_CAL_EN_TypeDef calEn;\n ADC1_ARG_WCR_TypeDef wcr;\n ADC1_ARG_KEY_TypeDef argKey;\n\n / Check channel range (16-31) /\n if ((channels & 0xFC00U) != channels)\n {\n g_ADC1_ErrorCode = HAL_INVALID_PARAM;\n return HAL_INVALID_PARAM;\n }\n\n / Enable calibration /\n calEn.U = ADC1_READ_REG(ADC1_CH_CAL_EN);\n\n / Enable each specified channel /\n if ((channels & 0x0001U) != 0U) calEn.B.CH16_CAL_EN = 1U;\n if ((channels & 0x0002U) != 0U) calEn.B.CH17_CAL_EN = 1U;\n if ((channels & 0x0004U) != 0U) calEn.B.CH18_CAL_EN = 1U;\n if ((channels & 0x0008U) != 0U) calEn.B.CH19_CAL_EN = 1U;\n if ((channels & 0x0010U) != 0U) calEn.B.CH20_CAL_EN = 1U;\n if ((channels & 0x0020U) != 0U) calEn.B.CH21_CAL_EN = 1U;\n if ((channels & 0x0040U) != 0U) calEn.B.CH22_CAL_EN = 1U;\n if ((channels & 0x0080U) != 0U) calEn.B.CH23_CAL_EN = 1U;\n if ((channels & 0x0100U) != 0U) calEn.B.CH24_CAL_EN = 1U;\n if ((channels & 0x0200U) != 0U) calEn.B.CH25_CAL_EN = 1U;\n if ((channels & 0x0400U) != 0U) calEn.B.CH26_CAL_EN = 1U;\n if ((channels & 0x0800U) != 0U) calEn.B.CH27_CAL_EN = 1U;\n if ((channels & 0x1000U) != 0U) calEn.B.CH28_CAL_EN = 1U;\n if ((channels & 0x2000U) != 0U) calEn.B.CH29_CAL_EN = 1U;\n if ((channels & 0x4000U) != 0U) calEn.B.CH30_CAL_EN = 1U;\n if ((channels & 0x8000U) != 0U) calEn.B.CH31_CAL_EN = 1U;\n\n ADC1_WRITE_REG(ADC1_CH_CAL_EN, calEn.U);\n\n return HAL_OK;\n}\n\nHAL_StatusTypeDef HAL_ADC1_DisableCalibration(void)\n{\n ADC1_CH_CAL_EN_TypeDef calEn;\n\n calEn.U = ADC1_READ_REG(ADC1_CH_CAL_EN);\n calEn.U = 0U;\n ADC1_WRITE_REG(ADC1_CH_CAL_EN, calEn.U);\n\n return HAL_OK;\n}\n\n/===========================================================/\n/ 13. PPU FUNCTIONS /\n/===========================================================/\n\nHAL_StatusTypeDef HAL_ADC1_EnablePPU(uint32_t channels)\n{\n ADC1_CH_IIR_EN_TypeDef iirEn;\n\n if ((channels & 0xFC00U) != channels)\n {\n g_ADC1_ErrorCode = HAL_INVALID_PARAM;\n return HAL_INVALID_PARAM;\n }\n\n iirEn.U = ADC1_READ_REG(ADC1_CH_IIR_EN);\n\n if ((channels & 0x0001U) != 0U) iirEn.B.CH16_IIR_EN = 1U;\n if ((channels & 0x0002U) != 0U) iirEn.B.CH17_IIR_EN = 1U;\n if ((channels & 0x0004U) != 0U) iirEn.B.CH18_IIR_EN = 1U;\n if ((channels & 0x0008U) != 0U) iirEn.B.CH19_IIR_EN = 1U;\n if ((channels & 0x0010U) != 0U) iirEn.B.CH20_IIR_EN = 1U;\n if ((channels & 0x0020U) != 0U) iirEn.B.CH21_IIR_EN = 1U;\n if ((channels & 0x0040U) != 0U) iirEn.B.CH22_IIR_EN = 1U;\n if ((channels & 0x0080U) != 0U) iirEn.B.CH23_IIR_EN = 1U;\n if ((channels & 0x0100U) != 0U) iirEn.B.CH24_IIR_EN = 1U;\n if ((channels & 0x0200U) != 0U) iirEn.B.CH25_IIR_EN = 1U;\n if ((channels & 0x0400U) != 0U) iirEn.B.CH26_IIR_EN = 1U;\n if ((channels & 0x0800U) != 0U) iirEn.B.CH27_IIR_EN = 1U;\n if ((channels & 0x1000U) != 0U) iirEn.B.CH28_IIR_EN = 1U;\n if ((channels & 0x2000U) != 0U) iirEn.B.CH29_IIR_EN = 1U;\n if ((channels & 0x4000U) != 0U) iirEn.B.CH30_IIR_EN = 1U;\n if ((channels & 0x8000U) != 0U) iirEn.B.CH31_IIR_EN = 1U;\n\n ADC1_WRITE_REG(ADC1_CH_IIR_EN, iirEn.U);\n\n return HAL_OK;\n}\n\nHAL_StatusTypeDef HAL_ADC1_DisablePPU(uint32_t channels)\n{\n ADC1_CH_IIR_EN_TypeDef iirEn;\n ADC1_PPU_IE_TypeDef ppuIE;\n\n iirEn.U = ADC1_READ_REG(ADC1_CH_IIR_EN);\n ppuIE.U = ADC1_READ_REG(ADC1_PPU_IE);\n\n / Disable IIR for specified channels */\n if ((channels & 0x0001U) != 0U)\n {\n iirEn.B.CH16_IIR_EN = 0U;\n ppuIE.B.INTEN_CH16_PU_HT = 0U;\n ppuIE.B.INTEN_CH16_PU_LT = 0U;\n }\n if ((channels & 0x0002U) != 0U)\n {\n iirEn.B.CH17_IIR_EN = 0U;\n ppuIE.B.INTEN_CH17_PU_HT = 0U;\n ppuIE.B.INTEN_CH17_PU_LT = 0U;\n }\n if ((channels & 0x0004U) != 0U)\n {\n iirEn.B.CH18_IIR_EN = 0U;\n ppuIE.B.INTEN_CH18_PU_HT = 0U;\n ppuIE.B.INTEN_CH18_PU_LT = 0U;\n }\n if ((channels & 0x0008U) != 0U)\n {\n iirEn.B.CH19_IIR_EN = 0U;\n ppuIE.B.INTEN_CH19_PU_HT = 0U;\n ppuIE.B.INTEN_CH19_PU_LT = 0U;\n }\n if ((channels & 0x0010U) != 0U)\n {\n iirEn.B.CH20_IIR_EN = 0U;\n ppuIE.B.INTEN_CH20_PU_HT = 0U;\n ppuIE.B.INTEN_CH20_PU_LT = 0U;\n }\n if ((channels & 0x0020U) != 0U)\n {\n iirEn.B.CH21_IIR_EN = 0U;\n ppuIE.B.INTEN_CH21_PU_HT = 0U;\n ppuIE.B.INTEN_CH21_PU_LT = 0U;\n }\n if ((channels & 0x0040U) != 0U)\n {\n iirEn.B.CH22_IIR_EN = 0U;\n ppuIE.B.INTEN_CH22_PU_HT = 0U;\n ppuIE.B.INTEN_CH22_PU_LT = 0U;\n }\n if ((channels & 0x0080U) != 0U)\n {\n iirEn.B.CH23_IIR_EN = 0U;\n ppuIE.B.INTEN_CH23_PU_HT = 0U;\n ppuIE.B.INTEN_CH23_PU_LT = 0U;\n }\n if ((channels & 0x0100U) != 0U)\n {\n iirEn.B.CH24_IIR_EN = 0U;\n ppuIE.B.INTEN_CH24_PU_HT = 0U;\n ppuIE.B.INTEN_CH24_PU_LT = 0U;\n }\n if ((channels & 0x0200U) != 0U)\n {\n iirEn.B.CH25_IIR_EN = 0U;\n ppuIE.B.INTEN_CH25_PU_HT = 0U;\n ppuIE.B.INTEN_CH25_PU_LT = 0U;\n }\n if ((channels & 0x0400U) != 0U)\n {\n iirEn.B.CH26_IIR_EN = 0U;\n ppuIE.B.INTEN_CH26_PU_HT = 0U;\n ppuIE.B.INTEN_CH26_PU_LT = 0U;\n }\n if ((channels & 0x0800U) != 0U)\n {\n iirEn.B.CH27_IIR_EN = 0U;\n ppuIE.B.INTEN_CH27_PU_HT = 0U;\n ppuIE.B.INTEN_CH27_PU_LT = 0U;\n }\n if ((channels & 0x1000U) != 0U)\n {\n iirEn.B.CH28_IIR_EN = 0U;\n ppuIE.B.INTEN_CH28_PU_HT = 0U;\n ppuIE.B.INTEN_CH28_PU_LT = 0U;\n }\n if ((channels & 0x2000U) != 0U)\n {\n iirEn.B.CH29_IIR_EN = 0U;\n ppuIE.B.INTEN_CH29_PU_HT = 0U;\n ppuIE.B.INTEN_CH29_PU_LT = 0U;\n }\n if ((channels & 0x4000U) != 0U)\n {\n iirEn.B.CH30_IIR_EN = 0U;\n ppuIE.B.INTEN_CH30_PU_HT = 0U;\n ppuIE.B.INTEN_CH30_PU_LT = 0U;\n }\n if ((channels & 0x8000U) != 0U)\n {\n iirEn.B.CH31_IIR_EN = 0U;\n ppuIE.B.INTEN_CH31_PU_HT = 0U;\n ppuIE.B.INTEN_CH31_PU_LT = 0U;\n }\n\n ADC1_WRITE_REG(ADC1_CH_IIR_EN, iirEn.U);\n ADC1_WRITE_REG(ADC1_PPU_IE, ppuIE.U);\n\n return HAL_OK;\n}\n\nHAL_StatusTypeDef HAL_ADC1_EnableIIR(uint32_t channels, uint8_t filterType)\n{\n ADC1_CH_IIR_CR_TypeDef iirCr;\n\n if (filterType > 3U)\n {\n g_ADC1_ErrorCode = HAL_INVALID_PARAM;\n return HAL_INVALID_PARAM;\n }\n\n iirCr.U = 0U;\n\n if ((channels & 0x0001U) != 0U) iirCr.B.CH16_IIR_CR = (uint32_t)filterType;\n if ((channels & 0x0002U) != 0U) iirCr.B.CH17_IIR_CR = (uint32_t)filterType;\n if ((channels & 0x0004U) != 0U) iirCr.B.CH18_IIR_CR = (uint32_t)filterType;\n if ((channels & 0x0008U) != 0U) iirCr.B.CH19_IIR_CR = (uint32_t)filterType;\n if ((channels & 0X0010U) != 0U) iirCr.B.CH20_IIR_CR = (uint32_t)filterType;\n if ((channels & 0X0020U) != 0U) iirCr.B.CH21_IIR_CR = (uint32_t)filterType;\n if ((channels & 0X0040U) != 0U) iirCr.B.CH22_IIR_CR = (uint32_t)filterType;\n if ((channels & 0X0080U) != 0U) iirCr.B.CH23_IIR_CR = (uint32_t)filterType;\n if ((channels & 0X0100U) != 0U) iirCr.B.CH24_IIR_CR = (uint32_t)filterType;\n if ((channels & 0X0200U) != 0U) iirCr.B.CH25_IIR_CR = (uint32_t)filterType;\n if ((channels & 0X0400U) != 0U) iirCr.B.CH26_IIR_CR = (uint32_t)filterType;\n if ((channels & 0X0800U) != 0U) iirCr.B.CH27_IIR_CR = (uint32_t)filterType;\n if ((channels & 0X1000U) != 0U) iirCr.B.CH28_IIR_CR = (uint32_t)filterType;\n if ((channels & 0X2000U) != 0U) iirCr.B.CH29_IIR_CR = (uint32_t)filterType;\n if ((channels & 0X4000U) != 0U) iirCr.B.CH30_IIR_CR = (uint32_t)filterType;\n if ((channels & 0X8000U) != 0U) iirCr.B.CH31_IIR_CR = (uint32_t)filterType;\n\n ADC1_WRITE_REG(ADC1_CH_IIR_CR, iirCr.U);\n\n return HAL_OK;\n}\n\nHAL_StatusTypeDef HAL_ADC1_DisableIIR(uint32_t channels)\n{\n ADC1_CH_IIR_EN_TypeDef iirEn;\n\n iirEn.U = ADC1_READ_REG(ADC1_CH_IIR_EN);\n\n if ((channels & 0x0001U) != 0U) iirEn.B.CH16_IIR_EN = 0U;\n if ((channels & 0x0002U) != 0U) iirEn.B.CH17_IIR_EN = 0U;\n if ((channels & 0x0004U) != 0U) iirEn.B.CH18_IIR_EN = 0U;\n if ((channels & 0x0008U) != 0U) iirEn.B.CH19_IIR_EN = 0U;\n if ((channels & 0x0010U) != 0U) iirEn.B.CH20_IIR_EN = 0U;\n if ((channels & 0x0020U) != 0U) iirEn.B.CH21_IIR_EN = 0U;\n if ((channels & 0x0040U) != 0U) iirEn.B.CH22_IIR_EN = 0U;\n if ((channels & 0x0080U) != 0U) iirEn.B.CH23_IIR_EN = 0U;\n if ((channels & 0x0100U) != 0U) iirEn.B.CH24_IIR_EN = 0U;\n if ((channels & 0x0200U) != 0U) iirEn.B.CH25_IIR_EN = 0U;\n if ((channels & 0x0400U) != 0U) iirEn.B.CH26_IIR_EN = 0U;\n if ((channels & 0x0800U) != 0U) iirEn.B.CH27_IIR_EN = 0U;\n if ((channels & 0x1000U) != 0U) iirEn.B.CH28_IIR_EN = 0U;\n if ((channels & 0x2000U) != 0U) iirEn.B.CH29_IIR_EN = 0U;\n if ((channels & 0x4000U) != 0U) iirEn.B.CH30_IIR_EN = 0U;\n if ((channels & 0x8000U) != 0U) iirEn.B.CH31_IIR_EN = 0U;\n\n ADC1_WRITE_REG(ADC1_CH_IIR_EN, iirEn.U);\n\n return HAL_OK;\n}\n\nHAL_StatusTypeDef HAL_ADC1_ConfigPPUWatchdog(uint32_t channels,\n uint8_t mode,\n int16_t lowThreshold,\n int16_t highThreshold,\n uint8_t lowHysteresis,\n uint8_t highHysteresis,\n uint8_t lowCounter,\n uint8_t highCounter)\n{\n ADC1_CH_AWD_MODE_TypeDef awdMode;\n ADC1_CH_AWD_HYST_LT_TypeDef hystLT;\n ADC1_CH_AWD_HYST_HT_TypeDef hystHT;\n ADC1_CH_AWD_NUM_LT0_TypeDef numLT;\n ADC1_CH_AWD_NUM_HT0_TypeDef numHT;\n\n if (mode > 3U || lowCounter > 7U || highCounter > 7U)\n {\n g_ADC1_ErrorCode = HAL_INVALID_PARAM;\n return HAL_INVALID_PARAM;\n }\n\n awdMode.U = 0U;\n if ((channels & 0x0001U) != 0U) awdMode.B.CH16_AWD_MODE = (uint32_t)mode;\n if ((channels & 0x0002U) != 0U) awdMode.B.CH17_AWD_MODE = (uint32_t)mode;\n if ((channels & 0x0004U) != 0U) awdMode.B.CH18_AWD_MODE = (uint32_t)mode;\n if ((channels & 0x0008U) != 0U) awdMode.B.CH19_AWD_MODE = (uint32_t)mode;\n if ((channels & 0x0010U) != 0U) awdMode.B.CH20_AWD_MODE = (uint32_t)mode;\n if ((channels & 0x0020U) != 0U) awdMode.B.CH21_AWD_MODE = (uint32_t)mode;\n if ((channels & 0x0040U) != 0U) awdMode.B.CH22_AWD_MODE = (uint32_t)mode;\n if ((channels & 0x0080U) != 0U) awdMode.B.CH23_AWD_MODE = (uint32_t)mode;\n if ((channels & 0x0100U) != 0U) awdMode.B.CH24_AWD_MODE = (uint32_t)mode;\n if ((channels & 0x0200U) != 0U) awdMode.B.CH25_AWD_MODE = (uint32_t)mode;\n if ((channels & 0x0400U) != 0U) awdMode.B.CH26_AWD_MODE = (uint32_t)mode;\n if ((channels & 0x0800U) != 0U) awdMode.B.CH27_AWD_MODE = (uint32_t)mode;\n if ((channels & 0x1000U) != 0U) awdMode.B.CH28_AWD_MODE = (uint32_t)mode;\n if ((channels & 0x2000U) != 0U) awdMode.B.CH29_AWD_MODE = (uint32_t)mode;\n if ((channels & 0x4000U) != 0U) awdMode.B.CH30_AWD_MODE = (uint32_t)mode;\n if ((channels & 0x8000U) != 0U) awdMode.B.CH31_AWD_MODE = (uint32_t)mode;\n\n hystLT.U = 0U;\n if ((channels & 0x0001U) != 0U) hystLT.B.CH16_AWD_HYST_LT = (uint32_t)lowHysteresis;\n if ((channels & 0x0002U) != 0U) hystLT.B.CH17_AWD_HYST_LT = (uint32_t)lowHysteresis;\n if ((channels & 0x0004U) != 0U) hystLT.B.CH18_AWD_HYST_LT = (uint32_t)lowHysteresis;\n if ((channels & 0x0008U) != 0U) hystLT.B.CH19_AWD_HYST_LT = (uint32_t)lowHysteresis;\n if ((channels & 0x0010U) != 0U) hystLT.B.CH20_AWD_HYST_LT = (uint32_t)lowHysteresis;\n if ((channels & 0x0020U) != 0U) hystLT.B.CH21_AWD_HYST_LT = (uint32_t)lowHysteresis;\n if ((channels & 0x0040U) != 0U) hystLT.B.CH22_AWD_HYST_LT = (uint32_t)lowHysteresis;\n if ((channels & 0x0080U) != 0U) hystLT.B.CH23_AWD_HYST_LT = (uint32_t)lowHysteresis;\n if ((channels & 0x0100U) != 0U) hystLT.B.CH24_AWD_HYST_LT = (uint32_t)lowHysteresis;\n if ((channels & 0x0200U) != 0U) hystLT.B.CH25_AWD_HYST_LT = (uint32_t)lowHysteresis;\n if ((channels & 0x0400U) != 0U) hystLT.B.CH26_AWD_HYST_LT = (uint32_t)lowHysteresis;\n if ((channels & 0x0800U) != 0U) hystLT.B.CH27_AWD_HYST_LT = (uint32_t)lowHysteresis;\n if ((channels & 0x1000U) != 0U) hystLT.B.CH28_AWD_HYST_LT = (uint32_t)lowHysteresis;\n if ((channels & 0x2000U) != 0U) hystLT.B.CH29_AWD_HYST_LT = (uint32_t)lowHysteresis;\n if ((channels & 0x4000U) != 0U) hystLT.B.CH30_AWD_HYST_LT = (uint32_t)lowHysteresis;\n if ((channels & 0x8000U) != 0U) hystLT.B.CH31_AWD_HYST_LT = (uint32_t)lowHysteresis;\n\n hystHT.U = 0U;\n if ((channels & 0x0001U) != 0U) hystHT.B.CH16_AWD_HYST_HT = (uint32_t)highHysteresis;\n if ((channels & 0x0002U) != 0U) hystHT.B.CH17_AWD_HYST_HT = (uint32_t)highHysteresis;\n if ((channels & 0x0004U) != 0U) hystHT.B.CH18_AWD_HYST_HT = (uint32_t)highHysteresis;\n if ((channels & 0x0008U) != 0U) hystHT.B.CH19_AWD_HYST_HT = (uint32_t)highHysteresis;\n if ((channels & 0x0010U) != 0U) hystHT.B.CH20_AWD_HYST_HT = (uint32_t)highHysteresis;\n if ((channels & 0x0020U) != 0U) hystHT.B.CH21_AWD_HYST_HT = (uint32_t)highHysteresis;\n if ((channels & 0x0040U) != 0U) hystHT.B.CH22_AWD_HYST_HT = (uint32_t)highHysteresis;\n if ((channels & 0x0080U) != 0U) hystHT.B.CH23_AWD_HYST_HT = (uint32_t)highHysteresis;\n if ((channels & 0x0100U) != 0U) hystHT.B.CH24_AWD_HYST_HT = (uint32_t)highHysteresis;\n if ((channels & 0x0200U) != 0U) hystHT.B.CH25_AWD_HYST_HT = (uint32_t)highHysteresis;\n if ((channels & 0x0400U) != 0U) hystHT.B.CH26_AWD_HYST_HT = (uint32_t)highHysteresis;\n if ((channels & 0x0800U) != 0U) hystHT.B.CH27_AWD_HYST_HT = (uint32_t)highHysteresis;\n if ((channels & 0x1000U) != 0U) hystHT.B.CH28_AWD_HYST_HT = (uint32_t)highHysteresis;\n if ((channels & 0x2000U) != 0U) hystHT.B.CH29_AWD_HYST_HT = (uint32_t)highHysteresis;\n if ((channels & 0x4000U) != 0U) hystHT.B.CH30_AWD_HYST_HT = (uint32_t)highHysteresis;\n if ((channels & 0x8000U) != 0U) hystHT.B.CH31_AWD_HYST_HT = (uint32_t)highHysteresis;\n\n numLT.U = 0U;\n numLT.B.CH16_AWD_NUM_LT0 = (uint32_t)lowCounter;\n numLT.B.CH17_AWD_NUM_LT0 = (uint32_t)lowCounter;\n numLT.B.CH18_AWD_NUM_LT0 = (uint32_t)lowCounter;\n numLT.B.CH19_AWD_NUM_LT0 = (uint32_t)lowCounter;\n numLT.B.CH20_AWD_NUM_LT0 = (uint32_t)lowCounter;\n numLT.B.CH21_AWD_NUM_LT0 = (uint32_t)lowCounter;\n numLT.B.CH22_AWD_NUM_LT0 = (uint32_t)lowCounter;\n numLT.B.CH23_AWD_NUM_LT0 = (uint32_t)lowCounter;\n numLT.B.CH24_AWD_NUM_LT0 = (uint32_t)lowCounter;\n numLT.B.CH25_AWD_NUM_LT0 = (uint32_t)lowCounter;\n numLT.B.CH26_AWD_NUM_LT0 = (uint32_t)lowCounter;\n numLT.B.CH27_AWD_NUM_LT0 = (uint32_t)lowCounter;\n numLT.B.CH28_AWD_NUM_LT0 = (uint32_t)lowCounter;\n numLT.B.CH29_AWD_NUM_LT0 = (uint32_t)lowCounter;\n numLT.B.CH30_AWD_NUM_LT0 = (uint32_t)lowCounter;\n numLT.B.CH31_AWD_NUM_LT0 = (uint32_t)lowCounter;\n\n numHT.U = 0U;\n numHT.B.CH16_AWD_NUM_HT0 = (uint32_t)highCounter;\n numHT.B.CH17_AWD_NUM_HT0 = (uint32_t)highCounter;\n numHT.B.CH18_AWD_NUM_HT0 = (uint32_t)highCounter;\n numHT.B.CH19_AWD_NUM_HT0 = (uint32_t)highCounter;\n numHT.B.CH20_AWD_NUM_HT0 = (uint32_t)highCounter;\n numHT.B.CH21_AWD_NUM_HT0 = (uint32_t)highCounter;\n numHT.B.CH22_AWD_NUM_HT0 = (uint32_t)highCounter;\n numHT.B.CH23_AWD_NUM_HT0 = (uint32_t)highCounter;\n numHT.B.CH24_AWD_NUM_HT0 = (uint32_t)highCounter;\n numHT.B.CH25_AWD_NUM_HT0 = (uint32_t)highCounter;\n numHT.B.CH26_AWD_NUM_HT0 = (uint32_t)highCounter;\n numHT.B.CH27_AWD_NUM_HT0 = (uint32_t)highCounter;\n numHT.B.CH28_AWD_NUM_HT0 = (uint32_t)highCounter;\n numHT.B.CH29_AWD_NUM_HT0 = (uint32_t)highCounter;\n numHT.B.CH30_AWD_NUM_HT0 = (uint32_t)highCounter;\n numHT.B.CH31_AWD_NUM_HT0 = (uint32_t)highCounter;\n\n ADC1_WRITE_REG(ADC1_CH_AWD_MODE, awdMode.U);\n ADC1_WRITE_REG(ADC1_CH_AWD_HYST_LT, hystLT.U);\n ADC1_WRITE_REG(ADC1_CH_AWD_HYST_HT, hystHT.U);\n ADC1_WRITE_REG(ADC1_CH_AWD_NUM_LT0, numLT.U);\n ADC1_WRITE_REG(ADC1_CH_AWD_NUM_HT0, numHT.U);\n\n return HAL_OK;\n}\n\nHAL_StatusTypeDef HAL_ADC1_EnablePPUWatchdogInterrupt(uint32_t channels,\n bool enableHighThresh,\n bool enableLowThresh)\n{\n ADC1_PPU_IE_TypeDef ppuIE;\n\n ppuIE.U = ADC1_READ_REG(ADC1_PPU_IE);\n\n if ((channels & 0x0001U) != 0U) ppuIE.B.INTEN_CH16_PU_HT = (uint32_t)enableHighThresh;\n if ((channels & 0x0002U) != 0U) ppuIE.B.INTEN_CH17_PU_HT = (uint32_t)enableHighThresh;\n if ((channels & 0x0004U) != 0U) ppuIE.B.INTEN_CH18_PU_HT = (uint32_t)enableHighThresh;\n if ((channels & 0x0008U) != 0U) ppuIE.B.INTEN_CH19_PU_HT = (uint32_t)enableHighThresh;\n if ((channels & 0x0010U) != 0U) ppuIE.B.INTEN_CH20_PU_HT = (uint32_t)enableHighThresh;\n if ((channels & 0x0020U) != 0U) ppuIE.B.INTEN_CH21_PU_HT = (uint32_t)enableHighThresh;\n if ((channels & 0x0040U) != 0U) ppuIE.B.INTEN_CH22_PU_HT = (uint32_t)enableHighThresh;\n if ((channels & 0x0080U) != 0U) ppuIE.B.INTEN_CH23_PU_HT = (uint32_t)enableHighThresh;\n if ((channels & 0x0100U) != 0U) ppuIE.B.INTEN_CH24_PU_HT = (uint32_t)enableHighThresh;\n if ((channels & 0x0200U) != 0U) ppuIE.B.INTEN_CH25_PU_HT = (uint32_t)enableHighThresh;\n if ((channels & 0x0400U) != 0U) ppuIE.B.INTEN_CH26_PU_HT = (uint32_t)enableHighThresh;\n if ((channels & 0x0800U) != 0U) ppuIE.B.INTEN_CH27_PU_HT = (uint32_t)enableHighThresh;\n if ((channels & 0x1000U) != 0U) ppuIE.B.INTEN_CH28_PU_HT = (uint32_t)enableHighThresh;\n if ((channels & 0x2000U) != 0U) ppuIE.B.INTEN_CH29_PU_HT = (uint32_t)enableHighThresh;\n if ((channels & 0x4000U) != 0U) ppuIE.B.INTEN_CH30_PU_HT = (uint32_t)enableHighThresh;\n if ((channels & 0x8000U) != 0U) ppuIE.B.INTEN_CH31_PU_HT = (uint32_t)enableHighThresh;\n\n if ((channels & 0x0001U) != 0U) ppuIE.B.INTEN_CH16_PU_LT = (uint32_t)enableLowThresh;\n if ((channels & 0x0002U) != 0U) ppuIE.B.INTEN_CH17_PU_LT = (uint32_t)enableLowThresh;\n if ((channels & 0x0004U) != 0U) ppuIE.B.INTEN_CH18_PU_LT = (uint32_t)enableLowThresh;\n if ((channels & 0x0008U) != 0U) ppuIE.B.INTEN_CH19_PU_LT = (uint32_t)enableLowThresh;\n if ((channels & 0x0010U) != 0U) ppuIE.B.INTEN_CH20_PU_LT = (uint32_t)enableLowThresh;\n if ((channels & 0x0020U) != 0U) ppuIE.B.INTEN_CH21_PU_LT = (uint32_t)enableLowThresh;\n if ((channels & 0x0040U) != 0U) ppuIE.B.INTEN_CH22_PU_LT = (uint32_t)enableLowThresh;\n if ((channels & 0x0080U) != 0U) ppuIE.B.INTEN_CH23_PU_LT = (uint32_t)enableLowThresh;\n if ((channels & 0x0100U) != 0U) ppuIE.B.INTEN_CH24_PU_LT = (uint32_t)enableLowThresh;\n if ((channels & 0x0200U) != 0U) ppuIE.B.INTEN_CH25_PU_LT = (uint32_t)enableLowThresh;\n if ((channels & 0x0400U) != 0U) ppuIE.B.INTEN_CH26_PU_LT = (uint32_t)enableLowThresh;\n if ((channels & 0x0800U) != 0U) ppuIE.B.INTEN_CH27_PU_LT = (uint32_t)enableLowThresh;\n if ((channels & 0x1000U) != 0U) ppuIE.B.INTEN_CH28_PU_LT = (uint32_t)enableLowThresh;\n if ((channels & 0x2000U) != 0U) ppuIE.B.INTEN_CH29_PU_LT = (uint32_t)enableLowThresh;\n if ((channels & 0x4000U) != 0U) ppuIE.B.INTEN_CH30_PU_LT = (uint32_t)enableLowThresh;\n if ((channels & 0x8000U) != 0U) ppuIE.B.INTEN_CH31_PU_LT = (uint32_t)enableLowThresh;\n\n ADC1_WRITE_REG(ADC1_PPU_IE, ppuIE.U);\n\n return HAL_OK;\n}\n\nHAL_StatusTypeDef HAL_ADC1_EnablePPUWatchdogChannelIRQ(uint8_t channel,\n bool enableHighThresh,\n bool enableLowThresh)\n{\n ADC1_PPU_IE_TypeDef ppuIE;\n\n if (channel < 16U || channel > 31U)\n {\n g_ADC1_ErrorCode = HAL_INVALID_PARAM;\n return HAL_INVALID_PARAM;\n }\n\n ppuIE.U = ADC1_READ_REG(ADC1_PPU_IE);\n\n if ((channel == 16U) || (channel == 30U) || (channel == 31U))\n {\n ppuIE.B.INTEN_CH16_PU_HT = (uint32_t)enableHighThresh;\n ppuIE.B.INTEN_CH16_PU_LT = (uint32_t)enableLowThresh;\n }\n else\n {\n const uint32_t offset = ((uint32_t)channel - 17U) / 2U;\n const uint8_t bit = ((uint32_t)channel - 17U) % 2U;\n\n if (bit == 0U)\n {\n ppuIE.B.INTEN_CH17_PU_HT = (uint32_t)enableHighThresh;\n ppuIE.B.INTEN_CH17_PU_LT = (uint32_t)enableLowThresh;\n }\n else\n {\n ppuIE.B.INTEN_CH18_PU_HT = (uint32_t)enableHighThresh;\n ppuIE.B.INTEN_CH18_PU_LT = (uint32_t)enableLowThresh;\n }\n\n ADC1_WRITE_REG(ADC1_PPU_IE, ppuIE.U);\n }\n\n return HAL_OK;\n}\n\nbool HAL_ADC1_IsTriggerOverrun(ADC_SequenceTypeDef sequence)\n{\n bool overrun = false;\n ADC1_IF0_TypeDef if0;\n\n if0.U = ADC1_READ_REG(ADC1_IF0);\n\n switch(sequence)\n {\n case ADC_SEQ_A:\n if (if0.B.INTSTS_ATRIG_OVERRUN != 0U) overrun = true;\n break;\n\n case ADC_SEQ_B:\n if (if0.B.INTSTS_BTRIG_OVERRUN != 0U) overrun = true;\n break;\n\n case ADC_SEQ_C:\n if (if0.B.INTSTS_CTRIG_OVERRUN != 0U) overrun = true;\n break;\n\n default:\n overrun = false;\n break;\n }\n\n return overrun;\n}\n\nbool HAL_ADC1_IsSingleShotMode(ADC_SequenceTypeDef sequence)\n{\n bool singleShot = false;\n\n switch(sequence)\n {\n case ADC_SEQ_A:\n if (g_ADC1_SeqAConfig.singleShot) singleShot = true;\n break;\n\n case ADC_SEQ_B:\n if (g_ADC1_SeqBConfig.singleShot) singleShot = true;\n break;\n\n case ADC_SEQ_C:\n if (g_ADC1_SeqCConfig.singleShot) singleShot = true;\n break;\n\n default:\n singleShot = false;\n break;\n }\n\n return singleShot;\n}\n\nbool HAL_ADC1_IsSequenceWorking(ADC_SequenceTypeDef sequence)\n{\n bool working = false;\n ADC1_SR0_TypeDef sr0;\n\n sr0.U = ADC1_READ_REG(ADC1_SR0);\n\n switch(sequence)\n {\n case ADC_SEQ_A:\n if (sr0.B.SEQA_WORK != 0U) working = true;\n break;\n\n case ADC_SEQ_B:\n if (sr0.B.SEQB_WORK != 0U) working = true;\n break;\n\n case ADC_SEQ_C:\n if (sr0.B.SEQC_WORK != 0U) working = true;\n break;\n\n default:\n working = false;\n break;\n }\n\n return working;\n}\n\nbool HAL_ADC1_IsAccumulationEnabled(ADC_SequenceTypeDef sequence)\n{\n if (sequence != ADC_SEQ_A)\n {\n return false;\n }\n\n return (bool)(ADC1_READ_REG(ADC1_CR0).B.SEQA_ACC_EN);\n}\n\nbool HAL_ADC1_IsDMAEnabled(ADC_SequenceTypeDef sequence)\n{\n bool dmaEnabled = false;\n\n switch(sequence)\n {\n case ADC_SEQ_A:\n dmaEnabled = (bool)(ADC1_READ_REG(ADC1_CR0).B.SEQA_DMA_EN);\n break;\n\n case ADC_SEQ_B:\n dmaEnabled = (bool)(ADC1_READ_REG(ADC1_CR0).B.SEQB_DMA_EN);\n break;\n\n case ADC_SEQ_C:\n dmaEnabled = (bool)(ADC1_READ_REG(ADC1_CR0).B.SEQC_DMA_EN);\n break;\n\n default:\n dmaEnabled = false;\n break;\n }\n\n return dmaEnabled;\n}\n\nADC_StateTypeDef HAL_ADC1_GetState(void)\n{\n return g_ADC1_State;\n}\n\nuint32_t HAL_ADC1_GetErrorCode(void)\n{\n return g_ADC1_ErrorCode;\n}\n\nuint8_t HAL_ADC1_GetCurrentChannel(ADC_SequenceTypeDef sequence)\n{\n uint8_t currentCh = 0U;\n ADC1_SR0_TypeDef sr0;\n\n sr0.U = ADC1_READ_REG(ADC1_SR0);\n\n switch(sequence)\n {\n case ADC_SEQ_A:\n case ADC_SEQ_B:\n case ADC_SEQ_C:\n currentCh = (uint8_t)sr0.B.ADC_CH;\n break;\n\n default:\n currentCh = 0U;\n break;\n }\n\n return currentCh;\n}\n\nuint32_t HAL_ADC1_GetCompletionCount(ADC_SequenceTypeDef sequence)\n{\n uint32_t count = 0U;\n ADC1_SR0_TypeDef sr0;\n\n sr0.U = ADC1_READ_REG(ADC1_SR0);\n\n switch(sequence)\n {\n case ADC_SEQ_A:\n count = (uint32_t)sr0.B.SEQA_CONT_CNT;\n break;\n\n case ADC_SEQ_B:\n count = (uint32_t)sr0.B.SEQA_CH_CNT;\n break;\n\n case ADC_SEQ_C:\n count = (uint32_t)sr0.B.SEQA_CH.
   Error message: JSON Parse error: Unterminated string]
   ▣ Sisyphus (Ultraworker) · GLM_4.7_30B_236 · 14m 7s
   [analyze-mode]
   ANALYSIS MODE. Gather context before diving deep:
   CONTEXT GATHERING (parallel):

   • 1-2 explore agents (codebase patterns, implementations)
   • 1-2 librarian agents (if external library involved)
   • Direct tools: Grep, AST-grep, LSP for targeted searches
     IF COMPLEX - DO NOT STRUGGLE ALONE. Consult specialists:
   • Oracle: Conventional problems (architecture, debugging, complex logic)
   • Artistry: Non-conventional problems (different approach needed)
     SYNTHESIZE findings before proceeding.

   ---

   为避免出错，这个生成文件可以分多个文件生成，以避免json解析出错
   理解了。为了避免JSON解析错误,我将分文件生成。现在开始生成第二个文件: adc1_hal.c 源码文件。
   我注意到之前的编辑器触发hook要求解释docstring的存在。

   Did the opencode hook throw this execption while it needed the docstring in output string and the output is tool long?
6. thdxr

   assigned

   jlongster

   and unassigned

   thdxr

   on Apr 26, 2026
7. thdxr

   removed

   bugSomething isn't workingSomething isn't working

   windows

   coreAnything pertaining to core functionality of the application (opencode server stuff)Anything pertaining to core functionality of the application (opencode server stuff)

   on May 3, 2026
8. github-actions commented on Jul 4, 2026

   

   github-actionsBot

   on Jul 4, 2026 – with GitHub Actions

   Contributor

   More actions

   To stay organized issues are automatically closed after 60 days of no activity. If the issue is still relevant please open a new one.
9. github-actions

   closed this as not plannedon Jul 4, 2026